Description:

This course provides an in-depth look at RISC-V architecture, from foundational ISA concepts to FPGA implementation. Participants will learn RISC-V encoding, compare RISC and CISC, and explore Harvard and Von Neumann designs. Topics include RV32I microarchitecture with single-cycle, multicycle, and pipelined designs. Hands-on sessions with Spike, Verilator, and Vivado software equip students to deploy RISC-V designs on FPGA platforms like the Arty A7, preparing them for real-world digital design applications.